1. Field of the Invention
The present invention relates to a variable resistance circuit. More particularly, the invention relates to a variable resistance circuit using MOS transistors.
2. Description of the Related Art
The variable resistance circuit using MOS transistors is described in “Design Principle of CMOS VLSI” by Neil H. E. Weste, Kamran Eshraghian (original authors), and Tomizawa Takashi, Matsuyama Yasuo (translation supervisors), the first edition, Maruzen, Aug. 30, 1988, p. 33–37.
A current Ids flowing in a MOS transistor in a linear region is expressed by the following equation by defining the gate length as L, the gate width as W, a voltage difference between the gate and the source as Vgs, a voltage difference between the drain and the source as Vds and a gain factor as K′.Ids=K′·(W/L)·{(Vgs−Vth)·Vds−Vds2/2}.
When (Vgs−Vth) is larger than Vds, the term of Vds2 can be ignored. The above equation Ids is expressed as follows.Ids=K′·(W/L)·(Vgs−Vth)·Vds Thus, the resistance is expressed as follows.1/{K′·(W/L)·(Vgs−Vth)}This resistance becomes a variable resistance of which resistance value can be controlled by Vgs.
In a variable resistance circuit particularly using a MOS transistor in a linear region, the bias voltage Vgs applied between the gate and the source needs to be set at least larger than (Vds+Vth), because the MOS transistor must be operated in the linear region and the gate voltage must be made equal to or larger than the sum of a voltage difference Vds generated across the resistance and the threshold voltage Vth of the MOS transistor.
On the other hand, the variable range of the resistance is limited within a range of a power supply voltage Vdd. For this reason, the voltage range which can be used for adjusting the resistance is limited within (Vdd−(Vds+Vth)) which is a difference between the power supply voltage and the minimum bias voltage necessary for operating the MOS transistor in the linear region. In this case, the ratio between the maximum and minimum values of the resistance of the MOS transistor, when the term of Vds2 is ignored, becomes (Vdd−Vds−Vth):Vds.
For example, when Vdd=5 V, Vth=0.7 V, Vds=0.5 V and the source voltage Vs=0 V, then the ratio=4.3:0.5. In recent years, the MOS transistor has been scaled down and breakdown voltage has also been decreased, thereby lowering the power supply voltage. Thus, the voltage range as the control voltage has also been reduced. When Vdd=3.3 V, the ratio=2.6:0.5.
FIG. 1 shows an example of a common variable resistance circuit 200.
The variable resistance circuit 200 is structured by a single N-type MOS transistor 201 (NMOS 77). Reference numeral 71 denotes a gain amplifier. Reference numeral 202 denotes an input terminal.
FIG. 2 shows a relationship between a gate voltage of the N-type MOS transistor 201 and a control signal voltage serving as a control signal 203.
FIG. 3 shows a relationship between a resistance value of a variable resistance observed at a pair of terminals D and S (204) and the control signal voltage.
When the maximum resistance value is defined as R0 and the minimum resistance value as R1, the ratio of the maximum value to the minimum value is R0/R1.
Even if the size of NMOS 77 is made n-fold so as to reduce the minimum resistance value to R1/n, since the maximum value of the resistance value becomes R0/n, the ratio is just R0/R1.
Accordingly, an object of the present invention is to provide a variable resistance circuit which enables the ratio of the maximum resistance value to the minimum resistance value to be large, while using a limited power supply voltage range as a control range.